This invention relates to hard drive circuitry, and more particularly relates to an apparatus for detecting an open circuit in a head write driver circuit.
Computer hard drive storage units are part of most computer systems. These units include a magnetic head that is maintained at a very small distance from, and directed across the surface of a rotating magnetic disk. The head is controlled to write data to, and read data from the disk. FIG. 1 is a high level diagram showing basic elements of a typical hard drive unit 10. A magnetic disk 12 spins on a spindle 14. An arm 16 is controllably moved about a pivot 18. The resulting movement causes a magnetic head 22, which is maintained a small distance from the surface of disk 12, to move across the disk 12 as shown by arrow 20. Differential data signals are provided on input lines 24 and 26 to hard drive circuitry 28. Included in hard drive circuitry 28 is write drive circuitry 30. Write drive signals are provided from write drive circuitry 30 on lines 32 and 34 to arm 16, where they are conveyed to magnetic head 22.
In write operations, differential signals of alternating polarity are provided via lines 32 and 34 to magnetic head 22 so as to magnetize disk 12 in a pattern representing data to be stored in the unit.
When wire 32 and/or wire 34 breaks, an open circuit condition results that prevents data from being written to disk 12. Obviously, this is undesirable, and as a result fault detection circuits have been devised for detecting such open circuit conditions, so that the user of the hard drive may be alerted to this situation. Such fault detection circuits are typically integrated into the write drive circuitry 30. One such fault detection circuit is disclosed in U.S. Pat. No. 5,729,208, which issued on Mar. 17, 1998, to Hisao Ogiwara, which is assigned to Texas Instruments Incorporated, and which is hereby incorporated by reference. FIG. 2 shows a prior art write drive circuit 30 including a fault detection circuit embodying principles from that patent. FIG. 3 is a signal timing diagram of certain signals used and generated by the circuit of FIG. 2.
Briefly, referring to both FIGS. 2 and 3, differential write data signals Dxand Dy, at positive supply emitter coupled logic (xe2x80x9cPECLxe2x80x9d) levels are provided on lines 42 and 44, respectively, and are converted to complementary metal oxide semiconductor (xe2x80x9cCMOSxe2x80x9d) levels in converter 46. The resulting level-adjusted data signals are inverted by inverters 48 and 50, respectively, and the resulting inverted data signals are provided as inputs to a write driver 52 and to a CMOS to PECL level converter 54. The reconverted data signal outputs of converter 54 are used as complementary phase control signals xcfx86 and xcfx86, respectively. The outputs of write driver 52, 32 and 34, carry the write driver signals HX and Hy, respectively, provided to the hard drive head 22 (FIG. 1). In FIG. 2 hard drive head 22 is not shown. However, the inductance LHEAD56 seen electrically by the write driver 52 is shown, as it is significant to a discussion of some of the signals shown in FIG. 3, as will be made clear below.
Line 32 is provided to one input of a first comparator 58, and line 34 is provided to one input of a second comparator 60. The other inputs of both comparators 58 and 60 are connected by a line 59 to the source 62 of a reference voltage Vth used to set the thresholds of comparators 58 and 60.
The differential outputs of comparator 58, carrying signals CX and {overscore (CX+L )}, are provided to the differential inputs of a latch 64. The differential clock inputs CK and {overscore (CK)} of latch 64 receive control signals {overscore (xcfx86)} and xcfx86, respectively. The differential outputs of latch 62, A and {overscore (A)}, are provided to two inputs of a 4-input multiplexer 66.
The differential outputs of comparator 60, carrying signals Cy and {overscore (CY+L )}, are provided to the differential inputs of a latch 68. The differential clock inputs CK and {overscore (CK)} of latch 68 receive control signals {overscore (xcfx86)} and xcfx86, respectively. The differential outputs of latch 68, B and {overscore (B)}, are provided to the other two inputs of 4-input multiplexer 66. Multiplexer 66 receives control signals xcfx86 and {overscore (xcfx86)} at the select input thereof.
The differential output of multiplexer 66 is provided to a PECL to CMOS level converter 70, the output of which is a WRITE OPEN indication signal.
Referring now additionally to FIG. 3, the write drive circuit 30 of FIG. 2 operates as follows. Write data DX and DY are logical opposites of one another, where one is high and the other low, and vice versa. DX and DY are converted to ECL levels by converter 46 into control signals xcfx86 and {overscore (xcfx86)} to be used to clock the latches 64 and 68 and multiplexer circuit 66. Write driver 52 then generates signals HX and HY from the write data, exemplary waveforms of which are shown in FIG. 3. Comparator 58 compares signal HX with reference voltage Vth, and generates differential output signals, signals CX and {overscore (CX+L )}. Comparator 60 compares signal HY with reference voltage Vth, and generates differential output signals, signals {overscore (CY+L )} and CY. The reference voltage Vth may be chosen to be a little higher than the saturation voltage of the comparators 58 and 60, which is between one and four volts. Signals CX and {overscore (CX+L )} are latched by latch 64, and signals CY and {overscore (CY +L )} are latched by latch 68, with control signals xcfx86 and {overscore (xcfx86)} serving as clock signals. In other words, the write driver data HX and HY are latched just before their predetermined polarity change by using, essentially, the rising edges of DX and DY as latch clocks.
It will be appreciated that during normal operation, the latch output signals, A and B, are always high or at logic level xe2x80x9cone.xe2x80x9d This is because the signals CX and CY are always latched at a logic xe2x80x9cone,xe2x80x9d as a consequence of the xe2x80x9creboundxe2x80x9d action of inductance LHEAD on the signals HX and HY. Thus, the WRITE OPEN signal is always high. However, if an open circuit condition occurs, as at time 80 in FIG. 3, the inductance LHEAD no longer operates on the signals HX and HY, and their waveform simply tracks that of DX and DY. Consequently a xe2x80x9czeroxe2x80x9d is latched in one of latches 64 and 68, in this case a xe2x80x9czeroxe2x80x9d level of signal CX being first latched in latch 64, and the WRITE OPEN signal goes to zero and remains there.
The foregoing solution has provided very good fault detection operation. However, as data rates of hard drives have increased with the advance of technology, certain problems have arisen in the operation of fault detection circuits like that circuit 30. Specifically, faults have been indicated when none exist, resulting in an incorrect determination of a failed hard drive unit.
How these faults occur can be better understood by reference to FIG. 4 and FIG. 5, which help illustrate two ways in which the circuit of FIG. 2 generates false fault indications. FIG. 4 shows two of the signals shown in FIG. 3, namely DX and HX, when the circuit 30 of FIG. 2 is operated at a high data rate typical for current hard drives. Note that the high level excursions, e.g., 90, and low level excursions, e.g., 92, of the data pules of DX are not of equal duration. After a relatively longer low excursion 94, at time 96, which is the occasion of a state latch in latch 64 (FIG. 2), it can be seen that at the level of HX has rebounded to a sufficiently positive level over the threshold level 98, for the reasons set forth above, so as to latch a xe2x80x9conexe2x80x9d in latch 64, resulting in a WRITE OPEN level indicating no fault. However, at time 100, after a relatively short low excursion 102, the level of HX has not yet rebounded to a level above the threshold level 98. As a result, a xe2x80x9czeroxe2x80x9d is latched in latch 64, causing the WRITE OPEN level to indicate a fault, even though no fault exists.
Another cause of false fault indications can be understood by reference to FIG. 5, which shows a portion of the circuit 30 of FIG. 2, with the circuit of comparator 58 shown in detail. It can be seen that line 32 from write driver 52, carrying drive signal HX, is connected to the base of an NPN bipolar transistor 110 in comparator 58. Line 32 is also connected to one end of the head inductance LHEAD 56, the other end of which is connected to line 34 from write driver 52, carrying drive signal HY. The emitter of bipolar transistor 110 is connected to one terminal of a current source 112, the other terminal of which is connected to ground. The emitter of bipolar transistor 110 is also connected to the emitter of a second NPN bipolar transistor 114. The common connection point of the emitter of bipolar transistor 110, the emitter of bipolar transistor 114, and of the connection terminal of current source 112 is node N1. The base of bipolar transistor 114 is connected by line 59 to source 62 of reference voltage Vth. The collector of bipolar transistor 112 is connected via resistor 116 to VCC, and to a line 118 carrying the signal {overscore (CX+L )} as an output of comparator 58 to latch 64. The collector of bipolar transistor 114 is connected via resistor 120 to VCC, and to a line 122 carrying the signal CX as an output of comparator 58 to latch 64.
Now, when write driver 52 switches, the voltage level of drive signal HX rises above the supply voltage VCC, due to the inductive effects from inductance LHEAD 56. This causes transistor 110 to saturate and voltage levels of signals CX and {overscore (CX+L )}, and the voltage at node N1, all to rise above VCC. The large inputs of signals CX and {overscore (CX+L )} to latch 64 can cause latch 64 to be set to the wrong state during writing.
Therefore, it is desired to have a hard drive unit with open circuit fault detection that operates reliably at modem hard drive data write rates.
In accordance with the present invention, there is provided an open circuit detection circuit for a hard disk drive write head, wherein the write head receives write drive signals from a write driver, and wherein the write driver generates a write drive signal in response to write control signals. The circuit includes a pulse width detector, generating a latch control signal in response to the detection of a write control signal having a predetermined duration. The circuit also includes a comparator comparing the write drive signal to a predetermined reference level and generating a comparison output signal indicative of whether the write driver signal is more or less than the predetermined level. A latch is coupled to receive the comparison output signal, the latch being clocked in response to the latch control signals. The latch output provides an indication of an open circuit.
These and other features of the invention will be apparent to those skilled in the art from the following detailed description of the invention, taken together with the accompanying drawings.